From Cyclotrons to Stockpiling: Mitigating Semiconductor Supply Chain Risks
Part 2 of a series focused on supply chains.
Welcome to SemiLiterate, a guide to the chip industry through the lens of public policy. For Part 1 of this series, click here.
BLUF: This post summarizes options for mitigating semiconductor supply chain risk. It argues there are two types of solutions: market-driven and government-driven. After reviewing broad solutions identified in public comments to BIS, strategies for mitigating risks to the semiconductor supply chain are reviewed. These strategies include stockpiling, increasing production/capacity (domestic or allied), developing substitutes, and recycling. Each option comes with constraints: basic availability, competing technology demand, political/regulatory/social factors, co-dependence on other markets, and producer diversity. There are no solutions, only tradeoffs.
In March 2020 the Bureau of Industry and Security posted a Request for Information (RFI) on “Risks in the Semiconductor Manufacturing and Advanced Packaging Supply Chain.” 96 comments were submitted. Comments were submitted by a wide range of companies, industry associations, and startups and included a striking amount of information about risks facing the semiconductor supply chain. Helpfully, they also included quite a bit of information about proposed solutions to mitigate these risks. This post summarizes proposed solutions, adding some context and analysis.
I ended Part 1 of this series on semiconductor supply chains by posing questions:
What tiers of what supply chains should a country focus on securing? Is it product-specific (memory chips?) or process-step (materials, EDA) specific?
What supply chain risks should be mitigated, what supply chain risks must be accepted because they are too expensive/expansive to mitigate?
When is the supply chain considered “secure”? Define the goal.
How broadly does one define supply chain security? Is human capital part of the supply chain? If so, what does it mean to “secure” it?
What role does regulation play as a risk in the semiconductor industry (ex. Kigali Amendment to the Montreal Protocol, Trusted Foundry program, EPA)?
The (partial) answer is: the government needs to identify semiconductor supply chain chokepoints for which there is no commercial or economic case for mitigating those chokepoints. Then, the government needs to provide incentives that buy-down the cost/risk associated with mitigating those chokepoints such that commercial firms re-align their operations to address that risk. The solution to semiconductor supply chain risks is market-driven but government-enabled.
Understanding the Risks:
To mitigate vulnerabilities, you have to first identify the risks. Part 1 of this series was focused on identifying a sub-set of semiconductor supply chain risks: single and sole source products or services whose interruption (deliberate or accidental) could disrupt semiconductor production. But there are many other types of risk affecting the chip industry, some of which were identified by commenters to BIS:
Company-Specific Risks: single/sole source suppliers, infrastructure failures, bankruptcies, counterfeiting, IP theft, product tampering, cybersecurity
Country-Specific Risks: currency manipulation, subsidies, predatory FDI, immigration restrictions, tariffs, standards/technical barriers to trade, environmental regulations, tax changes
Industry-Specific Risks: single/sole source suppliers, workforce/human capital, lack of adequate public infrastructure, innovation roadblocks
Regional Risks: natural disasters, geopolitics, armed conflict, expropriation
Mitigating Semiconductor Supply Chain Risk
Commenters to BIS identified two types of solutions to risks above:
Market-driven solutions are the sorts of supply chain mitigation the industry is capable of doing unilaterally, without support from the government, because there are economic incentives for following these best practices.
Government-led solutions, in contrast, are efforts for which economic incentives may be lacking but the strategic imperative is compelling enough that government funds/leadership can (and sometimes should) bridge the gap.
Fabs Exert a Gravitational Pull: multiple Taiwanese chemical and gas suppliers noted they were interested in building facilities in the United States to be in close geographic proximity to TSMC’s new Arizona fab. Fabs like suppliers to be near by. More fabs = greater upstream materials supply chain security.
Supply Chain Security Standards: Intel noted that it enforces an ISO standard on its suppliers. Large semiconductor companies can enforce supply chain best practices through their outsized importance to upstream suppliers.
Joint Development Projects: Multiple companies pointed to IMEC as the gold standard of public-private R&D partnerships in this industry. Modeling future pre-competitive innovation partnerships on IMEC’s best practices would result in enthusiastic company participation.
Corporate Strategic Investment Incentives: Most large semiconductor companies operate a venture capital arm to invest in promising startups (ex. Intel Capital, Applied Ventures). Finding ways to increase their investment in startups will help innovation.
Recycling: There is a tremendous amount of material waste in the semiconductor industry. Companies already recycle some materials to save money and increasing this practice would have derivative environmental and supply chain benefits.
Commenters proposed a huge variety of government-led solutions to semiconductor supply chain risks:
Talent programs: Commenters called for an expansion of SRC-DARPA JUMP: C-BRIC, SRC-NSF nCORE: CAPSL, SRC-NIST nCORE: NEW LIMITS), SRC: CHIRP, and NSF-SRC collaborations targeting semiconductor workforce development.
Database of Students Studying Chip-related fields: create a national database of students studying semiconductor-related fields for prospective employers to hire from.
Raw materials: strategic purchases and stockpiling of essential materials, chemicals, and gases used in semiconductor manufacturing, perhaps modeled along the lines of the Defense Logistics Agency’s Strategic Materials program, was suggested.
Purchase EOL equipment: U.S. government purchases of end-of-life semiconductor manufacturing equipment that is being sold by chip firms that no longer need it was suggested as a means to create a strategic stockpile.
Information Gathering and Assessment:
National Supply Chain Registry: create a national registry of information about supply chain risks and best practices affecting the chip industry.
Change how BIS TACs Function: Bureau of Industry and Security Technical Advisory Committees (TACs) could be re-vamped to provide technical information on supply chain security in addition to their normal function on export controls.
Regulatory Best Practices:
EPA Fab Permitting Efficiencies: the U.S. builds fabs far more slowly than the rest of the world due in part to delays in EPA permitting of factory construction. Commenters noted easing this regulatory burden would facilitate faster fab construction times.
Remove Tariffs on Chemicals and Silicon Ingot Pullers: There are apparently tariffs on several China-origin semiconductor-related products still in effect from the Section 301 tariffs. U.S. firms called for their removal.
Tax Credits and Abatements: A variety of commenters suggested tweaking the tax code to change how chip companies can depreciate the value of their equipment and other tax incentive strategies that would make it cheaper/easier to do business in the U.S. for the chip industry.
Copy Centers of Excellence: Commenters pointed to The Industrial Technology Research Institute (ITRI) of Taiwan, Fraunhofer Group for Microelectronics of Germany, IMEC of Belgium, and The Institute of Microelectronics (IME) of Singapore as models of innovative R&D partnerships whose structure is worth emulating.
SBIR Reform: commenters asserted the SBIR program is not designed to allow semiconductor and advanced packaging startups to invest in the capital needed to develop scalable manufacturing operations in the U.S. They suggested expanding matching fund programs like the SBIR Phase 2B program. This funding can support larger innovations long enough to get to a stage when they become ready for investors.
Manufacturing USA: Commenters were mixed - some called for Manufacturing USA funding to be increased, others criticized the programs as vulnerable to agenda-capture by large corporate members and lacking commercialization strategies.
NSF Reform: Commenters noted The National Science Foundation does not currently have a dedicated program for funding EDA research, and its investments in this area have declined over the past two decades. They recommended NSF fund additional research in to Electronic Photonic Co-Design EPDA tools.
Microelectronics Commons (DARPA): Commenters noted DARPA’s plans are still evolving with respect to developing a “Microelectronics Commons” as part of its Electronics Resurgence Initiative. ((DARPA-SN-21-06, Request for Information (RFI)). Commenters noted the need for a space for pre-competitive microelectronics innovation between companies and startups.
Build more fabs: self-explanatory. This is kinda the whole point of the exercise.
Rad Hard Test Facilities: there is an extreme deficit of radiation hardness test infrastructure nationally and this presents a chokepoint for OSAT of electronics that need to be tested for radiation hardness before they are assembled in to products bound for radiation saturated environments (space). With companies like SpaceX, Project Kuiper, and Blue Origin all launching more electronics in to space, demand for these testing services is expect to grow dramatically and will necessitate construction of new cyclotrons. Commenters pointed out need for new infrastructure.
Diversify Geographic Concentration of Talent, Water, Electricity: A typical semiconductor production facility uses ~2-5 million gallons of water per day. A large production facility can use up to 30-50 megawatts of peak electrical capacity, enough to power a small city. Commenters suggested maybe not building new fabs in deserts.
There Are No Solutions, Only Tradeoffs
A lot of these ideas are good in theory and might work in a vacuum (absent competition and innovation), but every solution comes with tradeoffs.
Regulation is going to make or break efforts to mitigate semiconductor supply chain risk
The EPA permitting process for fab construction creates huge delays. The Department of Interior restricts mining on federal lands which hold deposits of materials needed for semiconductor manufacturing. USTR still has tariffs on some semiconductor-related products from China. The EPA regulates the use of many chemicals used in semiconductor manufacturing, increasing costs and injecting uncertainty. US immigration policies keep talent from staying in the U.S. or even entering the country. BLM is selling down the Federal Helium Reserve. The Biden Administration has committed the U.S. to the Kigali Amendment to the Montreal Protocol, which will effectively limit how much the U.S. chip industry can use hydrofluorocarbons going forward (an intensively consumed, but environmentally problematic, gas). All of these regulations raise the cost of doing business as a chip company in the U.S. and could undermine semiconductor supply chain resiliency efforts.
Innovation < Fabrication
We’ve already talked about how the CHIPS Act prioritizes funding for new fabrication over new innovation. The Act will help large corporations become more globally competitive, but these companies will not necessarily fulfill the needs of the US government nor invent the future of non-CMOS semiconductors. Commenters point out again and again the traditional way the government funds R&D (DARPA, NSF, SBIR, Manufacturing USA, OTAs) are not creating the conditions this industry needs for innovation but are instead mainly benefitting large established companies. There needs to be more emphasis on innovation. Comments from one startup in particular highlight this problem:
When we started our EUV [chemical] development work there were two facilities that we considered as development partners: the now defunct SEMATECH (Albany, New York) and IMEC (Leuven, Belgium). These two facilities employed very different engagement models when we were selecting our development partner. SEMATECH’s business model at that time required a significant upfront membership fee in order to do even the most preliminary of work. These fees were cost prohibitive for a startup of our size and level of funding at that time. In comparison, IMEC proactively approached us with creative ways to engage in zero dollar (free to us) Joint Development Projects (JDP) and we continued working under this arrangement for a full four years before we executed our first paid JDP with IMEC. Since 2014 we have maintained a team of assignees who work onsite at IMEC and perform critical work to test and analyze our products on these tools.
The biggest US semiconductor supply chain risk is that the ~$50 billion soon to be appropriated for the CHIPS Act gets spent on building factories that make today’s semiconductors and fail to invent tomorrow’s future. Its always harder to come up with solutions than point out problems. This RFI from BIS illustrates this point clearly: commenters had lots of ideas about what is wrong, and far fewer ideas about how to fix it. Any effort to increase US semiconductor supply chain resilience has to propose ways that change firm behavior: from establishing a microelectronics commons to provide no-cost JDPs to building a new heavy ion cyclotron, the government needs policies that buy-down risk in ways that favorably re-align commercial incentives.